CMOS integrated circuits typically include inverting buffer circuits therein for driving on-chip and off-chip loads. As illustrated by FIG. 1, a conventional CMOS inverting buffer circuit includes a PMOS pull-up transistor T1 and an NMOS pull-down transistor T2 which are electrically connected in series between a power supply voltage (Vcc) and a ground or negative reference voltage (Vss).
Unfortunately, although the buffer circuit of FIG. 1 can be designed to switch at relatively high speeds, it requires a large amount current from its power supply when switching a capacitive load C.sub.L from Vss to Vcc and then back to Vss. For example, a large total charge Q=C.sub.L (Vcc) is required from the power supply to switch each capacitive load C.sub.L through an entire pull-up and pull-down cycle. Accordingly, if an integrated circuit has a large number of buffer circuits therein that frequently switch appreciable loads, the amount of switching current required from the power supply may be substantial.